S912XEG128J2MAA Datasheet, PDF (476/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
Table 11-4. CRGFLG Field Descriptions
Field
7
RTIF
6
PORF
5
LVRF
4
LOCKIF
3
LOCK
2
ILAF
1
SCMIF
0
SCM
Description
Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.
Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
IPLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
Lock Status Bit — LOCK reflects the current state of IPLL lock condition. This bit is cleared in Self Clock Mode.
Writes have no effect.
0 VCOCLK is not within the desired tolerance of the target frequency.
1 VCOCLK is within the desired tolerance of the target frequency.
Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block
Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Illegal address reset has not occurred.
1 Illegal address reset has occurred.
Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be
cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request.
0 No change in SCM bit.
1 SCM bit has changed.
Self Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
0 MCU is operating normally with OSCCLK available.
1 MCU is operating in Self Clock Mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK
running at its minimum frequency f_SCM.
11.3.2.5 S12XECRG Interrupt Enable Register (CRGINT)
This register enables S12XECRG interrupt requests.
Module Base + 0x0004
7
6
R
0
RTIE
W
5
4
3
0
0
LOCKIE
2
1
0
0
0
SCMIE
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-7. S12XECRG Interrupt Enable Register (CRGINT)
MC9S12XE-Family Reference Manual Rev. 1.25
476
Freescale Semiconductor