S912XEG128J2MAA Datasheet, PDF (484/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
Table 11-13. COP Watchdog Rates⁽¹⁾
CR2
CR1
CR0
OSCCLK
Cycles to Timeout
1
1
1
2 ²⁴
1. OSCCLK cycles are referenced from the previous COP time-out reset
(writing $55/$AA to the ARMCOP register)
11.3.2.10 Reserved Register (FORBYP)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
modes can alter the S12XECRG’s functionality.
Module Base + 0x0009
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-12. Reserved Register (FORBYP)
Read: Always read $00 except in special modes
Write: Only in special modes
11.3.2.11 Reserved Register (CTCTL)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special test
modes can alter the S12XECRG’s functionality.
Module Base + 0x000A
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-13. Reserved Register (CTCTL)
Read: Always read $00 except in special modes
MC9S12XE-Family Reference Manual Rev. 1.25
484
Freescale Semiconductor