S912XEG128J2MAA Datasheet, PDF (524/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
Only analog input signals within the potential range of V_RL to V_RH (A/D reference potentials) will result
in a non-railed digital output code.
13.4.2 Digital Sub-Block
This subsection explains some of the digital features in more detail. See Section 13.3.2, “Register
Descriptions” for all details.
13.4.2.1 External Trigger Input
The external trigger feature allows the user to synchronize ATD conversions to the external environment
events rather than relying on software to signal the ATD module when ATD conversions are to take place.
The external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to
be edge or level sensitive with polarity control. Table 13-23 gives a brief description of the different
combinations of control bits and their effect on the external trigger function.
ETRIGLE
X
X
0
0
1
1
Table 13-23. External Trigger Control Bits
ETRIGP
X
X
0
1
0
1
ETRIGE
0
0
1
1
1
1
SCAN
Description
0
Ignores external trigger. Performs one
conversion sequence and stops.
1
Ignores external trigger. Performs
continuous conversion sequences.
X
Falling edge triggered. Performs one
conversion sequence per trigger.
X
Rising edge triggered. Performs one
conversion sequence per trigger.
X
Trigger active low. Performs continuous
conversions while trigger is active.
X
Trigger active high. Performs continuous
conversions while trigger is active.
During a conversion, if additional active edges are detected the overrun error flag ETORF is set.
In either level or edge triggered modes, the first conversion begins when the trigger is received.
Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be
triggered externally.
If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion
sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger is left asserted in
level mode while a sequence is completing, another sequence will be triggered immediately.
MC9S12XE-Family Reference Manual Rev. 1.25
524
Freescale Semiconductor