S912XEG128J2MAA Datasheet, PDF (1293/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix E Detailed Register Address Map
Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued)
Address Name
Extended ID R
0xXX0x ^{CANxTIDR1 W}
XX10 Standard ID R
W
Extended ID R
CANxTIDR2 W
0xXX12
Standard ID R
W
Extended ID R
CANxTIDR3 W
0xXX13
Standard ID R
W
0xXX14
–
0xXX1B
CANxTDSR0– ^R
CANxTDSR7 ^W
R
0xXX1C CANxTDLR
W
R
0xXX1D CANxTTBPR
W
R
0xXX1E CANxTTSRH
W
R
0xXX1F CANxTTSRL
W
Bit 7
ID20
ID2
ID14
ID6
DB7
PRIO7
TSR15
TSR7
Bit 6
ID19
ID1
ID13
ID5
DB6
PRIO6
TSR14
TSR6
Bit 5
ID18
ID0
ID12
ID4
DB5
PRIO5
TSR13
TSR5
Bit 4
SRR=1
RTR
ID11
ID3
DB4
PRIO4
TSR12
TSR4
Bit 3
IDE=1
IDE=0
ID10
ID2
DB3
DLC3
PRIO3
TSR11
TSR3
Bit 2
ID17
ID9
ID1
DB2
DLC2
PRIO2
TSR10
TSR2
Bit 1
ID16
ID8
ID0
DB1
DLC1
PRIO1
TSR9
TSR1
Bit 0
ID15
ID7
RTR
DB0
DLC0
PRIO0
TSR8
TSR0
Freescale Semiconductor
MC9S12XE-Family Reference Manual Rev. 1.25
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