S912XEG128J2MAA Datasheet, PDF (127/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-28. DDRS Register Field Descriptions
Field
7-0
DDRS
Description
Port S data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port S pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTS or PTIS registers, when changing the
DDRS register.
2.3.32 Port S Reduced Drive Register (RDRS)
Address 0x024B
R
W
Reset
7
RDRS7
0
1. Read: Anytime.
Write: Anytime.
6
RDRS6
5
RDRS5
4
RDRS4
3
RDRS3
2
RDRS2
0
0
0
0
0
Figure 2-30. Port S Reduced Drive Register (RDRS)
Access: User read/write⁽¹⁾
1
0
RDRS1
RDRS0
0
0
Table 2-29. RDRS Register Field Descriptions
Field
7-0
RDRS
Description
Port S reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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