S912XEG128J2MAA Datasheet, PDF (500/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12 Pierce Oscillator (S12XOSCLCPV2)
12.1.3 Block Diagram
Figure 12-1 shows a block diagram of the XOSC.
Clock
Monitor
Monitor_Failure
OSCCLK
Peak
Detector
Gain Control
V_DDPLL = 1.8 V
EXTAL
Rf
XTAL
Figure 12-1. XOSC Block Diagram
12.2 External Signal Description
This section lists and describes the signals that connect off chip
12.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins
Theses pins provides operating voltage (V_DDPLL) and ground (V_SSPLL) for the XOSC circuitry. This
allows the supply voltage to the XOSC to use an independent bypass capacitor.
12.2.2 EXTAL and XTAL — Input and Output Pins
These pins provide the interface for either a crystal or a 1.8V CMOS compatible clock to control the
internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator
amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived
MC9S12XE-Family Reference Manual Rev. 1.25
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Freescale Semiconductor