S912XEG128J2MAA Datasheet, PDF (117/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-15. RDRIV Register Field Descriptions (continued)
Field
1
RDPB
0
RDPA
Description
Port B reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all output pins as either full or reduced independent of the function used on
the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Port A reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all output pins as either full or reduced independent of the function used on
the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
2.3.15 ECLK Control Register (ECLKCTL)
Address 0x001C (PRR)
Access: User read/write⁽¹⁾
7
R
NECLK
W
6
NCLKX2
5
DIV16
4
EDIV4
3
EDIV3
2
EDIV2
1
EDIV1
0
EDIV0
Mode
Reset⁽²⁾: Depen-
1
0
0
0
0
0
0
dent
SS
0
1
0
0
0
0
0
0
ES
1
1
0
0
0
0
0
0
ST
0
1
0
0
0
0
0
0
EX
0
1
0
0
0
0
0
0
NS
1
1
0
0
0
0
0
0
NX
0
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-13. ECLK Control Register (ECLKCTL)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
2. Reset values in emulation modes are identical to those of the target mode.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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