S912XEG128J2MAA Datasheet, PDF (718/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are
concatenated, channel 0 registers become the high order bytes of the double byte channel.
When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel
clock select control bits. That is channel 7 when channels 6 and 7 are concatenated, channel 5 when
channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when
channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order
8-bit channel as also shown in Figure 19-24. The polarity of the resulting PWM output is controlled by the
PPOLx bit of the corresponding low order 8-bit channel as well.
MC9S12XE-Family Reference Manual Rev. 1.25
718
Freescale Semiconductor