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| S912XEG128J2MAA Datasheet, PDF (106/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 2 Port Integration Module (S12XEPIMV1)
Register
Name
Bit 7
6
5
4
0x0378 R
PTF W
PTF7
PTF6
PTF5
PTF4
0x0379 R
PTIF W
PTIF7
0x037A R
DDRF W DDRF7
0x037B R
RDRF W RDRF7
PTIF6
DDRF6
RDRF6
PTIF5
DDRF5
RDRF5
PTIF4
DDRF4
RDRF4
0x037C R
PERF W PERF7
0x037D R
PPSF W PPSF7
0x037E R
0
Reserved W
PERF6
PPSF6
0
PERF5
PPSF5
0
PERF4
PPSF4
0
0x037F R
0
PTFRR W
0
PTFRR5 PTFRR4
= Unimplemented or Reserved
3
PTF3
PTIF3
DDRF3
RDRF3
PERF3
PPSF3
0
PTFRR3
2
PTF2
PTIF2
DDRF2
RDRF2
PERF2
PPSF2
0
PTFRR2
1
PTF1
PTIF1
DDRF1
RDRF1
PERF1
PPSF1
0
PTFRR1
Bit 0
PTF0
PTIF0
DDRF0
RDRF0
PERF0
PPSF0
0
PTFRR0
2.3.2 Register Descriptions
The following table summarizes the effect of the various conï¬guration bits, i.e. data direction (DDR),
output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS) on the pin function and pull
device activity.
The conï¬guration bit PS is used for two purposes:
1. Conï¬gure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
MC9S12XE-Family Reference Manual Rev. 1.25
106
Freescale Semiconductor
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