S912XEG128J2MAA Datasheet, PDF (175/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.102 Port F Input Register (PTIF)
Chapter 2 Port Integration Module (S12XEPIMV1)
Address 0x0379
7
R PTIF7
6
PTIF6
5
PTIF5
4
PTIF4
3
PTIF3
2
PTIF2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
1. Read: Anytime.
Figure 2-100. Port F Input Register (PTIF)
Write:Never, writes to this register have no effect.
Access: User read⁽¹⁾
1
PTIF1
0
PTIF0
u
u
Field
7-0
PTIF
Table 2-97. PTIF Register Field Descriptions
Description
Port F input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.103 Port F Data Direction Register (DDRF)
Address 0x037A
R
W
Reset
7
DDRF7
0
1. Read: Anytime.
Write: Anytime.
6
DDRF6
5
DDRF5
4
DDRF4
3
DDRF3
2
DDRF2
0
0
0
0
0
Figure 2-101. Port F Data Direction Register (DDRF)
Access: User read/write⁽¹⁾
1
0
DDRF1
DDRF0
0
0
Table 2-98. DDRF Register Field Descriptions
Field
7-0
DDRF
Description
Port F data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port F pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
175