S912XEG128J2MAA Datasheet, PDF (204/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Memory Mapping Control (S12XMMCV4)
Global Address [22:0]
0
0 1 0 0 ^{Bit17 Bit16}
Bit10 Bit9
Bit0
EPAGE Register [7:0]
Address [9:0]
Address: CPU Local Address
or BDM Local Address
Figure 3-16. EPAGE Address Mapping
Field
7–0
EP[7:0]
Table 3-15. EPAGE Field Descriptions
Description
EEPROM Page Index Bits 7–0 — These page index bits are used to select which of the 256 EEPROM array
pages is to be accessed in the EEPROM Page Window.
The reset value of 0xFE ensures that there is a linear EEPROM space available between addresses 0x0800
and 0x0FFF out of reset.
The fixed 1K page 0x0C00–0x0FFF of EEPROM is equivalent to page 255 (page number 0xFF).
3.4 Functional Description
The MMC block performs several basic functions of the S12X sub-system operation: MCU operation
modes, priority control, address mapping, select signal generation and access limitations for the system.
Each aspect is described in the following subsections.
3.4.1 MCU Operating Mode
• Normal single-chip mode
There is no external bus in this mode. The MCU program is executed from the internal memory
and no external accesses are allowed.
• Special single-chip mode
This mode is generally used for debugging single-chip operation, boot-strapping or security related
operations. The active background debug mode is in control of the CPU code execution and the
BDM firmware is waiting for serial commands sent through the BKGD pin. There is no external
bus in this mode.
MC9S12XE-Family Reference Manual Rev. 1.25
204
Freescale Semiconductor