S912XEG128J2MAA Datasheet, PDF (593/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
15.3.1.6 IIC Control Register 2(IBCR2)
Module Base + 0x0005
R
W
Reset
7
GCEN
0
6
5
4
3
2
0
0
0
ADTYPE
ADR10
0
0
0
0
0
Figure 15-9. IIC Bus Control Register 2(IBCR2)
1
ADR9
0
0
ADR8
0
This register contains the variables used in general call and in ten-bit address.
Read and write anytime
Table 15-10. IBCR2 Field Descriptions
Field
Description
7
GCEN
General Call Enable.
0 General call is disabled. The module dont receive any general call data and address.
1 enable general call. It indicates that the module can receive address and any data.
6
ADTYPE
Address Type— This bit selects the address length. The variable must be configured correctly before IIC enters
slave mode.
0 7-bit address
1 10-bit address
5,4,3 Reserved — Bit 5,4 and 3 of the IBCR2 are reserved for future compatibility. These bits will always read 0.
RESERVED
2:0
Slave Address [10:8] —These 3 bits represent the MSB of the 10-bit address when address type is asserted
ADR[10:8] (ADTYPE = 1).
15.4 Functional Description
This section provides a complete functional description of the IICV3.
15.4.1 I-Bus Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. Logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer and STOP signal. They are described briefly in the following sections and illustrated in
Figure 15-10.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
593