S912XEG128J2MAA Datasheet, PDF (1091/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

2. FDIV shown generates an FCLK frequency of 1.05 MHz
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2)
28.3.2.2 Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Offset Module Base + 0x0001
R
W
Reset
7
6
5
4
3
2
KEYEN[1:0]
RNV[5:2]
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 28-6. Flash Security Register (FSEC)
1
0
SEC[1:0]
F
F
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0x7F_FF0F located in P-Flash memory (see Table 28-3) as
indicated by reset condition F in Figure 28-6. If a double bit fault is detected while reading the P-Flash
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be
set to leave the Flash module in a secured state with backdoor key access disabled.
Table 28-10. FSEC Field Descriptions
Field
Description
7–6
Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the
KEYEN[1:0] Flash module as shown in Table 28-11.
5–2
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.
RNV[5:2}
1–0
Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 28-12. If the
SEC[1:0] Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
Table 28-11. Flash KEYEN States
KEYEN[1:0]
Status of Backdoor Key Access
00
DISABLED
01
DISABLED⁽¹⁾
10
ENABLED
11
DISABLED
1. Preferred KEYEN state to disable backdoor key access.
Freescale Semiconductor
MC9S12XE-Family Reference Manual Rev. 1.25
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