S912XEG128J2MAA Datasheet, PDF (141/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.50
Chapter 2 Port Integration Module (S12XEPIMV1)
Port P Polarity Select Register (PPSP)
Address 0x025D
R
W
Reset
7
PPSP7
0
1. Read: Anytime.
Write: Anytime.
6
PPSP6
5
PPSP5
4
PPSP4
3
PPSP3
2
PPSP2
0
0
0
0
0
Figure 2-48. Port P Polarity Select Register (PPSP)
Access: User read/write⁽¹⁾
1
0
PPSP1
PPSP0
0
0
Table 2-46. PPSP Register Field Descriptions
Field
7-0
PPSP
Description
Port P pull device select—Determine pull device polarity on input pins
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-
up or pull-down device if enabled.
1 A rising edge on the associated Port P pin sets the associated flag bit in the PIFP register. A pull-down device is
connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
0 A falling edge on the associated Port P pin sets the associated flag bit in the PIFP register.A pull-up device is
connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
2.3.51 Port P Interrupt Enable Register (PIEP)
Read: Anytime.
Address 0x025E
R
W
Reset
7
PIEP7
0
1. Read: Anytime.
Write: Anytime.
6
PIEP6
5
PIEP5
4
PIEP4
3
PIEP3
2
PIEP2
0
0
0
0
0
Figure 2-49. Port P Interrupt Enable Register (PIEP)
Access: User read/write⁽¹⁾
1
0
PIEP1
PIEP0
0
0
Field
7-0
PIEP
Table 2-47. PPSP Register Field Descriptions
Description
Port P interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
141