S912XEG128J2MAA Datasheet, PDF (371/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 XGATE (S12XGATEV3)
10.3.1.14 XGATE Register 2 (XGR2)
The XGR2 register (Figure 10-16) provides access to the RISC core’s register 2.
Module Base +0x00024
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
XGR2
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-16. XGATE Register 2 (XGR2)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-16. XGR2 Field Descriptions
Field
Description
15–0
XGATE Register 2 — The RISC core’s register 2
XGR2[15:0]
10.3.1.15 XGATE Register 3 (XGR3)
The XGR3 register (Figure 10-17) provides access to the RISC core’s register 3.
Module Base +0x00026
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
XGR3
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-17. XGATE Register 3 (XGR3)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-17. XGR3 Field Descriptions
Field
Description
15–0
XGATE Register 3 — The RISC core’s register 3
XGR3[15:0]
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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