S912XEG128J2MAA Datasheet, PDF (111/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.8 Port D Data Register (PORTD)
Chapter 2 Port Integration Module (S12XEPIMV1)
Address 0x0005 (PRR)
Access: User read/write⁽¹⁾
7
R
PD7
W
6
PD6
5
PD5
4
PD4
3
PD3
2
PD2
1
PD1
0
PD0
Altern.
Function
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Reset
0
0
0
0
0
0
0
0
Figure 2-6. Port D Data Register (PORTD)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Field
7-0
PD
Table 2-9. PORTD Register Field Descriptions
Description
Port D general purpose input/output data—Data Register
Port D pins 7 through 0 are associated with data I/O lines DATA[7:0] respectively in expanded modes.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2.3.9 Port C Data Direction Register (DDRC)
Address 0x0006 (PRR)
Access: User read/write⁽¹⁾
7
R
DDRC7
W
6
DDRC6
5
DDRC5
4
DDRC4
3
DDRC3
2
DDRC2
1
DDRC1
0
DDRC0
Reset
0
0
0
0
0
0
0
0
Figure 2-7. Port C Data Direction Register (DDRC)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
111