S912XEG128J2MAA Datasheet, PDF (1244/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
In Table A-28 the timing characteristics for master mode are listed.
Table A-28. SPI Master Mode Timing Characteristics
Num C
Characteristic
1
D SCK frequency
1
D SCK period
2
D Enable lead time
3
D Enable lag time
4
D Clock (SCK) high or low time
5
D Data setup time (inputs)
6
D Data hold time (inputs)
9
D Data valid after SCK edge
10
D Data valid after SS fall (CPHA = 0)
11
D Data hold time (outputs)
12
D Rise and fall time inputs
13
D Rise and fall time outputs
1. See Figure A-9.
Symbol
Min
Typ
f_sck
1/2048
—
t_sck
2¹
—
t_lead
—
1/2
t_lag
—
1/2
t_wsck
—
1/2
t_su
8
—
t_hi
8
—
t_vsck
—
—
t_vss
—
—
t_ho
0
—
t_rfi
—
—
t_rfo
—
—
Max
1/2⁽¹⁾
2048
—
—
—
—
—
15
15
—
8
8
Unit
f_bus
t_bus
t_sck
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
f_SCK/f_bus
1/2
1/4
5
10 ¹⁵ 20 ²⁵ 30 ³⁵ 40
f_bus [MHz]
Figure A-9. Derating of maximum f_SCK to f_bus ratio in Master Mode
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MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor