S912XEG128J2MAA Datasheet, PDF (377/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 XGATE (S12XGATEV3)
set_xgsem: 1 is written to XGSEM[n] (and 1 is written to XGSEMM[n])
clr_xgsem: 0 is written to XGSEM[n] (and 1 is written to XGSEMM[n])
ssem:
Executing SSEM instruction (on semaphore n)
csem:
Executing CSEM instruction (on semaphore n)
clr_xgsem
csem
LOCKED BY
S12X_CPU
LOCKED BY
XGATE
clr_xgsem
ssem &
set_xgsem
csem
ssem
UNLOCKED
ssem & set_xgsem
Figure 10-24. Semaphore State Transitions
Figure 10-25 gives an example of the typical usage of the XGATE hardware semaphores.
Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is
running on the RISC core. They both have a critical section of code that accesses the same system resource.
To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence
must be embedded in a semaphore lock/release sequence as shown.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
377