S912XEG128J2MAA Datasheet, PDF (523/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
Table 13-22. Conversion result mapping to ATDDRn
A/D
resolution
DJM
conversion result mapping to
ATDDRn
8-bit data 0 Bit[11:4] = result, Bit[3:0]=0000
8-bit data 1 Bit[7:0] = result, Bit[11:8]=0000
10-bit data 0 Bit[11:2] = result, Bit[1:0]=00
10-bit data 1 Bit[9:0] = result, Bit[11:10]=00
12-bit data X Bit[11:0] = result
13.4 Functional Description
The ADC12B16C is structured into an analog sub-block and a digital sub-block.
13.4.1 Analog Sub-Block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies V_DDA and V_SSA allow to isolate noise of other MCU circuitry from the analog sub-block.
13.4.1.1 Sample and Hold Machine
The Sample and Hold (S/H) Machine accepts analog signals from the external world and stores them as
capacitor charge on a storage node.
During the sample process the analog input connects directly to the storage node.
The input analog signals are unipolar and must fall within the potential range of V_SSA to V_DDA.
During the hold process the analog input is disconnected from the storage node.
13.4.1.2 Analog Input Multiplexer
The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold
machine.
13.4.1.3 Analog-to-Digital (A/D) Machine
The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8
or 10 or 12 bits. The A/D machine uses a successive approximation architecture. It functions by comparing
the stored analog sample potential with a series of digitally generated analog potentials. By following a
binary search algorithm, the A/D machine locates the approximating potential that is nearest to the
sampled potential.
When not converting the A/D machine is automatically powered down.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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