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S912XEG128J2MAA Datasheet, PDF (539/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Table 14-7. TSCR1 Field Descriptions (continued)
Field
5
TSFRZ
4
TFFCA
3
PRNT
Description
Timer and Modulus Counter Stop While in Freeze Mode
0 Allows the timer and modulus counter to continue running while in freeze mode.
1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation.
The pulse accumulators do not stop in freeze mode.
Timer Fast Flag Clear All
0 Allows the timer ï¬ag clearing to function normally.
1 A read from an input capture or a write to the output compare channel registers causes the corresponding
channel ï¬ag, CxF, to be cleared in the TFLG1 register. Any access to the TCNT register clears the TOF ï¬ag
in the TFLG2 register. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF ï¬ags in the
PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF ï¬ag in the PBFLG register.
Any access to the MCCNT register clears the MCZF ï¬ag in the MCFLG register. This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental ï¬ag
clearing due to unintended accesses.
Note: The ï¬ags cannot be cleared via the normal ï¬ag clearing mechanism (writing a one to the ï¬ag) when
TFFCA = 1.
Precision Timer
0 Enables legacy timer. Only bits DLY0 and DLY1 of the DLYCT register are used for the delay selection of the
delay counter. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection.
MCPR0 and MCPR1 bits of the MCCTL register are used for modulus down counter prescaler selection.
1 Enables precision timer. All bits in the DLYCT register are used for the delay selection, all bits of the PTPSR
register are used for Precision Timer Prescaler Selection, and all bits of PTMCPSR register are used for the
prescaler Precision Timer Modulus Counter Prescaler selection.
14.3.2.7 Timer Toggle On Overï¬ow Register 1 (TTOV)
Module Base + 0x0007
R
W
Reset
7
TOV7
0
6
TOV6
5
TOV5
4
TOV4
3
TOV3
2
TOV2
0
0
0
0
0
Figure 14-10. Timer Toggle On Overï¬ow Register 1 (TTOV)
Read or write: Anytime
All bits reset to zero.
1
TOV1
0
0
TOV0
0
Table 14-8. TTOV Field Descriptions
Field
Description
7:0
TOV[7:0]
Toggle On Overï¬ow Bits â TOV97:0] toggles output compare pin on timer counter overï¬ow. This feature only
takes effect when in output compare mode. When set, it takes precedence over forced output compare but not
channel 7 override events.
0 Toggle output compare pin on overï¬ow feature disabled.
1 Toggle output compare pin on overï¬ow feature enabled.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
539
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