S912XEG128J2MAA Datasheet, PDF (176/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTF or PTIF registers, when changing the
DDRF register.
2.3.104 Port F Reduced Drive Register (RDRF)
Address 0x037B
R
W
Reset
7
RDRF7
0
1. Read: Anytime.
Write: Anytime.
6
RDRF6
5
RDRF5
4
RDRF4
3
RDRF3
2
RDRF2
0
0
0
0
0
Figure 2-102. Port F Reduced Drive Register (RDRF)
Access: User read/write⁽¹⁾
1
0
RDRF1
RDRF0
0
0
Table 2-99. RDRF Register Field Descriptions
Field
7-0
RDRF
Description
Port F reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
2.3.105 Port F Pull Device Enable Register (PERF)
Address 0x037C
R
W
Reset
7
PERF7
1
1. Read: Anytime.
Write: Anytime.
6
PERF6
5
PERF5
4
PERF4
3
PERF3
2
PERF2
Access: User read/write⁽¹⁾
1
0
PERF1
PERF0
1
1
1
1
1
1
1
Figure 2-103. Port F Pull Device Enable Register (PERF)
Table 2-100. PERF Register Field Descriptions
Field
7-0
PERF
Description
Port F pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.
MC9S12XE-Family Reference Manual Rev. 1.25
176
Freescale Semiconductor