S912XEG128J2MAA Datasheet, PDF (123/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTT or PTIT registers, when changing the
DDRT register.
2.3.24 Port T Reduced Drive Register (RDRT)
Address 0x0243
R
W
Reset
7
RDRT7
0
1. Read: Anytime.
Write: Anytime.
6
RDRT6
5
RDRT5
4
RDRT4
3
RDRT3
2
RDRT2
0
0
0
0
0
Figure 2-22. Port T Reduced Drive Register (RDRT)
Access: User read/write⁽¹⁾
1
0
RDRT1
RDRT0
0
0
Table 2-23. RDRT Register Field Descriptions
Field
7-0
RDRT
Description
Port T reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
2.3.25 Port T Pull Device Enable Register (PERT)
Address 0x0244
R
W
Reset
7
PERT7
0
1. Read: Anytime.
Write: Anytime.
6
PERT6
5
PERT5
4
PERT4
3
PERT3
2
PERT2
Access: User read/write⁽¹⁾
1
0
PERT1
PERT0
0
0
0
0
0
0
0
Figure 2-23. Port T Pull Device Enable Register (PERT)
Table 2-24. PERT Register Field Descriptions
Field
7-0
PERT
Description
Port T pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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