S912XEG128J2MAA Datasheet, PDF (1033/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
Table 27-16. FERCNFG Field Descriptions (continued)
Field
Description
3
ERSVIE1
2
ERSVIE0
1
DFDIE
0
SFDIE
EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 27.3.2.8)
EEE Error Type 0 Interrupt Enable — The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see Section 27.3.2.8)
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 27.3.2.8)
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 27.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see Section 27.3.2.8)
27.3.2.7 Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
Offset Module Base + 0x0006
R
W
Reset
7
CCIF
1
6
5
4
3
2
0
MGBUSY
RSVD
ACCERR
FPVIOL
0
0
0
0
0
1
0
MGSTAT[1:0]
0⁽¹⁾
0¹
= Unimplemented or Reserved
Figure 27-11. Flash Status Register (FSTAT)
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 27.6).
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Freescale Semiconductor
MC9S12XE-Family Reference Manual Rev. 1.25
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