S912XEG128J2MAA Datasheet, PDF (821/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 23 Voltage Regulator (S12VREGL3V3V1)
Table 23-3. VREGHTCL Field Descriptions
Field
Description
7, 6
Reserved
5
VSEL
4
VAE
3
HTEN
2
HTDS
1
HTIE
0
HTIF
These reserved bits are used for test purposes and writable only in special modes.
They must remain clear for correct temperature sensor operation.
Voltage Access Select Bit — If set, the bandgap reference voltage V_BG can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). The internal access must be enabled by bit VAE.
See device level specification for connectivity.
0 An internal temperature proportional voltage V_HT can be accessed internally if VAE is set.
1 Bandgap reference voltage V_BG can be accessed internally if VAE is set.
Voltage Access Enable Bit — If set, the voltage selected by bit VSEL can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). See device level specification for connectivity.
0 Voltage selected by VSEL can not be accessed internally (i.e. External analog input is connected to Analog
to Digital Converter channel).
1 Voltage selected by VSEL can be accessed internally.
High Temperature Enable Bit — If set the temperature sense is enabled.
0 The temperature sense is disabled.
1 The temperature sense is enabled.
High Temperature Detect Status Bit —
This read-only status bit reflects the temperature status. Writes have no effect.
0 Temperature T_DIE is below level T_HTID or RPM or Shutdown Mode.
1 Temperature T_DIE is above level T_HTIA and FPM.
High Temperature Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever HTIF is set.
High Temperature Interrupt Flag — HTIF — High Temperature Interrupt Flag
HTIF is set to 1 when HTDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no
effect. If enabled (HTIE=1), HTIF causes an interrupt request.
0 No change in HTDS bit.
1 HTDS bit has changed.
Note: On entering the reduced power mode the HTIF is not cleared by the VREG.
23.3.2.2 Control Register (VREGCTRL)
The VREGCTRL register allows the configuration of the VREG_3V3 low-voltage detect features.
0x02F1
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
2
1
0
0
LVDS
LVIE
LVIF
0
0
0
0
Figure 23-3. Control Register (VREGCTRL)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
821