S912XEG128J2MAA Datasheet, PDF (387/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 XGATE (S12XGATEV3)
10.8.2.5 Bit Field Operations
This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The
width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is
ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions
are very useful to extract, insert, clear, set or toggle portions of a 16 bit word
7
43
0
W4
O4
RS2
15
5
20
W4=3, O4=2
RS1
Bit Field Extract
Bit Field Insert
15
3
0
RD
BFEXT
Figure 10-26. Bit Field Addressing
R3,R4,R5 ; R5: W4+1 bits with offset O4, will be extracted from R4 into R3
10.8.2.6 Special Instructions for DMA Usage
The XGATE offers a number of additional instructions for flag manipulation, program flow control and
debugging:
1. SIF: Set a channel interrupt flag
2. SSEM: Test and set a hardware semaphore
3. CSEM: Clear a hardware semaphore
4. BRK: Software breakpoint
5. NOP: No Operation
6. RTS: Terminate the current thread
10.8.3 Cycle Notation
Table 10-23 show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each
letter implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals
are not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible
every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit
operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
387