S912XEG128J2MAA Datasheet, PDF (152/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-59. DDRJ Register Field Descriptions (continued)
Field
1
DDRJ
0
DDRJ
Description
Port J data direction—
This register controls the data direction of pin 1.
The enabled SCI2 forces the I/O state to be an output. The DDRM bits revert to controlling the I/O direction of a pin
when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 0.
The enabled SCI3 or CS3 signal forces the I/O state to be an output. In those cases the data direction bits will not
change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.
2.3.64 Port J Reduced Drive Register (RDRJ)
Address 0x026B
R
W
Reset
7
RDRJ7
0
1. Read: Anytime.
Write: Anytime.
6
RDRJ6
5
RDRJ5
4
RDRJ4
3
RDRJ3
2
RDRJ2
0
0
0
0
0
Figure 2-62. Port J Reduced Drive Register (RDRJ)
Access: User read/write⁽¹⁾
1
0
RDRJ1
RDRJ0
0
0
Table 2-60. RDRJ Register Field Descriptions
Field
7-0
RDRJ
Description
Port J reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
MC9S12XE-Family Reference Manual Rev. 1.25
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