S912XEG128J2MAA Datasheet, PDF (1236/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
V
V_DDR,
V_DDX
Figure A-4. MC9S12XE-Family Power Sequencing
V_DDA
>= 0
t
During power sequencing V_DDA can be powered up before V_DDR, V_DDX.
V_DDR and V_DDX must be powered up together adhering to the operating conditions differential.
V_RH power up must follow V_DDA to avoid current injection.
A.6 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for oscillator and
phase-locked loop (PLL).
A.6.1 Startup
Table A-23 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the Clock and Reset Generator (CRG) block description
Table A-23. Startup Characteristics
Conditions are shown in Table A-4unless otherwise noted
Num C
Rating
Symbol
Min
Typ
1 D Reset input pulse width, minimum input time
PW_RSTL
2
—
2 D Startup from reset
t_RST
192
—
3 D Wait recovery startup time
t_WRS
—
—
4 D Fast wakeup from STOP⁽²⁾
t_fws
—
50
1. This is the time between RESET deassertion and start of CPU code execution.
2. Including voltage regulator startup; V_DD /V_DDF filter capacitors 220 nF, V_DD35 = 5 V, T= 25°C
Max
—
4000⁽¹⁾
14
100
Unit
t_osc
n_bus
t_cyc
µs
A.6.1.1 POR
The release level V_PORR and the assert level V_PORA are derived from the V_DD supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t_CQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n_uposc.
1236
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor