S912XEG128J2MAA Datasheet, PDF (179/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-103. Register availability per port⁽¹⁾
Port Data
Input
Data Reduced Pull
Direction Drive Enable
Polarity
Select
A
yes
-
yes
yes
yes
-
B
yes
-
yes
-
C
yes
-
yes
-
D
yes
-
yes
-
E
yes
-
yes
-
K
yes
-
yes
-
T
yes
yes
yes
yes
yes
yes
S
yes
yes
yes
yes
yes
yes
M
yes
yes
yes
yes
yes
yes
P
yes
yes
yes
yes
yes
yes
H
yes
yes
yes
yes
yes
yes
J
yes
yes
yes
yes
yes
yes
AD0
yes
-
yes
yes
yes
-
AD1
yes
-
yes
yes
yes
-
R
yes
yes
yes
yes
yes
yes
L
yes
yes
yes
yes
yes
yes
F
yes
yes
yes
yes
yes
yes
1. Each cell represents one register with individual configuration bits
Wired- Interrupt Interrupt
Or Mode Enable Flag
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
yes
-
-
yes
-
-
-
yes
yes
-
yes
yes
-
yes
yes
-
-
-
-
-
-
-
-
-
yes
-
-
-
-
-
Routing
-
-
-
-
-
-
-
yes
yes
-
-
-
-
-
-
yes
yes
2.4.2.1 Data register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration (Figure 2-107).
2.4.2.2 Input register (PTIx)
This is a read-only register and always returns the buffered state of the pin (Figure 2-107).
2.4.2.3 Data direction register (DDRx)
This register defines whether the pin is used as an input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-107).
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
179