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S912XEG128J2MAA Datasheet, PDF (369/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 10 XGATE (S12XGATEV3)
Table 10-12. XGSEM Field Descriptions
Field
Description
15â8
Semaphore Mask â These bits control the write access to the XGSEM bits.
XGSEMM[7:0] Read:
These bits will always read "0".
Write:
0 Disable write access to the XGSEM in the same bus cycle
1 Enable write access to the XGSEM in the same bus cycle
7â0
XGSEM[7:0]
Semaphore Bits â These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can
be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same
write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the
XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access.
Read:
0 Semaphore is unlocked or locked by the RISC core
1 Semaphore is locked by the S12X_CPU
Write:
0 Clear semaphore if it was locked by the S12X_CPU
1 Attempt to lock semaphore by the S12X_CPU
10.3.1.11 XGATE Condition Code Register (XGCCR)
The XGCCR register (Figure 10-13) provides access to the RISC coreâs condition code register.
Module Base +0x001D
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
XGN
0
2
XGZ
0
1
XGV
0
Figure 10-13. XGATE Condition Code Register (XGCCR)
0
XGC
0
Read: In debug mode if unsecured and not idle (XGCHID â 0x00)
Write: In debug mode if unsecured and not idle (XGCHID â 0x00)
Table 10-13. XGCCR Field Descriptions
Field
3
XGN
2
XGZ
1
XGV
0
XGC
Sign Flag â The RISC coreâs Sign ï¬ag
Description
Zero Flag â The RISC coreâs Zero ï¬ag
Overï¬ow Flag â The RISC coreâs Overï¬ow ï¬ag
Carry Flag â The RISC coreâs Carry ï¬ag
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
369
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