S912XEG128J2MAA Datasheet, PDF (258/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 External Bus Interface (S12XEBIV4)
state operation (stretching) of the external bus access is done in emulation modes when accessing internal
memory or emulation memory addresses.
In both modes observation of the internal operation is supported through the external bus (internal
visibility).
5.5.2.1 Example 2a: Emulation Single-Chip Mode
This mode is used for emulation systems in which the target application is operating in normal single-chip
mode.
Figure 5-5 shows the PRU connection with the available external bus signals in an emulator application.
S12X_EBI
ADDR[22:0]/IVD[15:0]
DATA[15:0]
Emulator
EMULMEM
LSTRB
RW
PRU
PRR
Ports
ADDR[22:20]/ACC[2:0]
ADDR[19:16]/
IQSTAT[3:0]
ECLK
ECLKX2
Figure 5-5. Application in Emulation Single-Chip Mode
The timing diagram for this operation is shown in:
• Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’
The associated timing numbers are given in:
• Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAIT disabled)’
Timing considerations:
• Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing.
• LSTRB has the same timing as RW.
MC9S12XE-Family Reference Manual Rev. 1.25
258
Freescale Semiconductor