S912XEG128J2MAA Datasheet, PDF (233/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Memory Protection Unit (S12XMPUV1)
4.3.1.4 MPU Address Status Register 2 (MPUASTAT2)
Address: Module Base + 0x0003
7
6
5
4
3
2
1
0
R
ADDR[7:0]
W
Reset
0
0
0
0
0
0
0
0
Figure 4-6. MPU Address Status Register (MPUASTAT2)
Read: Anytime
Write: Never
Table 4-6. MPUASTAT2 Field Descriptions
Field
Description
7–0
ADDR[7:0]
Access violation address bits — The ADDR[7:0] bits contain bits [7:0] of the global address which caused
the current access violation interrupt. These bits are undefined if the access error flag bit (AEF) in the MPUFLG
register is not set.
4.3.1.5 MPU Descriptor Select Register (MPUSEL)
Address: Module Base + 0x0005
7
6
5
4
3
2
1
0
R
0
0
0
0
SVSEN
W
SEL[2:0]
Reset
0
0
0
0
0
0
0
0
Figure 4-7. MPU Descriptor Select Register (MPUSEL)
Read: Anytime
Write: Anytime
Table 4-7. MPUSEL Field Descriptions
Field
7
SVSEN
2–0
SEL[2:0]
Description
MPU supervisor state enable bit — This bit enables the memory protection for the CPU in supervisor state.
If this bit is cleared, the MPU does not affect any accesses coming from the CPU in supervisor state. This is to
prevent the CPU from locking out itself while configuring the protection descriptors (during initialization after a
system reset and during the update of the protection descriptors for a task switch). The memory protection
functionality for the other bus-masters is unaffected by this bit.
0 MPU is disabled for the CPU in supervisor state
1 MPU is enabled for the CPU in supervisor state
Descriptor select bits — The SEL[2:0] bits select which descriptor is visible in the MPU Descriptor Register
window (MPUDESC0—MPUDESC5).
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
233