S912XEG128J2MAA Datasheet, PDF (87/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 Device Overview MC9S12XE-Family
1.9 MPU Configuration
The MPU has the option of a third bus master (CPU + XGATE + other) which is not present on this device
family but may be on other parts.
1.10 VREG Configuration
The VREGEN connection of the voltage regulator is tied internally to VDDR such that the voltage
regulator is always enabled with VDDR connected to a positive supply voltage. The device must be
configured with the internal voltage regulator enabled. Operation in conjunction with an external voltage
regulator is not supported.
The autonomous periodic interrupt clock output is mapped to PortT[5].
The API trimming register APITR is loaded on rising edge of RESET from the Flash IFR option field at
global address 0x40_00F0 bits[5:0] during the reset sequence. Currently factory programming of this IFR
range is not supported.
1.10.1 Temperature Sensor Configuration
The VREG high temperature trimming register bits VREGHTTR[3:0] are loaded from the internal Flash
during the reset sequence. To use the high temperature interrupt within the specified limits (T_HTIA and
T_HTID) these bits must be loaded with 0x8. Currently factory programming is not supported.
The device temperature can be monitored on ADC0 channel[17].
The internal bandgap reference voltage can also be mapped to ADC0 analog input channel[17]. The
voltage regulator VSEL bit when set, maps the bandgap and, when clear, maps the temperature sensor to
ADC0 channel[17].
Read access to reserved VREG register space returns “0”. Write accesses have no effect. This device does
not support access abort of reserved VREG register space.
1.11 BDM Clock Configuration
The BDM alternate clock source is the oscillator clock.
1.12 S12XEPIM Configuration
On smaller derivatives the S12XEPIM module is a subset of the S12XEP100. The registers of the
unavailable ports are unimplemented.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
87