S912XEG128J2MAA Datasheet, PDF (354/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 XGATE (S12XGATEV3)
XGATE Channel ID
A 7-bit identifier associated with an XGATE channel. In S12XE designs valid Channel IDs range
from $0D to $78.
XGATE Priority Level
A priority ranging from 1 to 7 which is associated with an XGATE channel. The priority level of
an XGATE channel is selected in the S12X_INT module.
XGATE Register Bank
A register bank consists of registers R1-R7, CCR and the PC. Each interrupt level is associated with
one register bank.
XGATE Channel Interrupt
An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module.
XGATE Software Channel
Special XGATE channel that is not associated with any peripheral service request. A Software
Channel is triggered by its Software Trigger Bit which is implemented in the XGATE module.
XGATE Semaphore
A set of hardware flip-flops that can be exclusively set by either the S12X_CPU or the XGATE.
(see Section 10.4.4, “Semaphores”)
XGATE Thread
A code sequence which is executed by the XGATE’s RISC core after receiving an XGATE request.
XGATE Debug Mode
A special mode in which the XGATE’s RISC core is halted for debug purposes. This mode enables
the XGATE’s debug features (see Section 10.6, “Debug Mode”).
XGATE Software Error
The XGATE is able to detect a number of error conditions caused by erratic software (see
Section 10.4.5, “Software Error Detection”). These error conditions will cause the XGATE to seize
program execution and flag an Interrupt to the S12X_CPU.
Word
A 16 bit entity.
Byte
An 8 bit entity.
10.1.2 Features
The XGATE module includes these features:
• Data movement between various targets (i.e. Flash, RAM, and peripheral modules)
• Data manipulation through built in RISC core
MC9S12XE-Family Reference Manual Rev. 1.25
354
Freescale Semiconductor