XRT79L71_1 Datasheet, PDF (98/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
Receive E3 Configuration and Status Register # 1 - G.751 (Address = 0x1110)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
RxFERF
Algo
Unused
R/O
R/O
R/O
R/W
R/O
R/O
0
0
0
0
0
0
BIT 1
R/O
0
REV. 1.0.0
BIT 0
RxBIP-4
Enable
R/W
0
BIT NUMBER
NAME
7-5
Unused
4
RxFERF Algo
3-1
0
Unused
RxBIP4 Enable
TYPE
R/O
R/W
R/O
R/W
DESCRIPTION
Receive FERF Algorithm Select:
This READ/WRITE bit-field permits the user to select the FERF
Defect Declaration and Clearance criteria that will be used by the
Receive E3 Framer block.
0 - The FERF/RDI defect is declared if the "A" bit-field (within the
incoming E3 data-stream) is set to "1" for 3 consecutive frames.
The FERF/RDI defect is cleared if the "A" bit-field is set to "0" for
3 consecutive frames.
1 - The FERF/RDI defect is declared if the "A" bit-field is set to
"1" for 5 consecutive frames. The FERF/RDI defect is cleared if
the "A" bit-field is set to "0" for 5 consecutive frames.
NOTE: This bit-field is ignored if Bit 0 (RxBIP-4 Enable) is set to
"1".
Enable BIP-4 Verification:
This READ/WRITE bit-field permits the user to configure the
Receive E3 Framer block to verify the BIP-4 value, within the
incoming E3 data-stream. If the user implements this configura-
tion selection, then all of the following will be true.
a. The Receive E3 Framer block will detect and flag
occurrences of BIP-4 errors within the incoming E3 data-
stream.
b. The Receive E3 Framer block will never declare the
FERF/RDI indicator.
c. The Receive E3 Framer block will interpret the "A" bit,
being set "High" to indicate a FEBE/REI event (in lieu of a
FERF/RDI condition).
The user can enable or disable BIP-4 verification as depicted
below.0 - BIP-4 Verification is NOT performed.1 - BIP-4 Verifica-
tion is performed.
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