XRT79L71_1 Datasheet, PDF (57/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
6-4
Chunk_Size[2:0]/RxFIFO
Packet Fill Level[2:0]
TYPE
R/W
DESCRIPTION
Chunk_Size[2:0]/RxFIFO Packet Fill Level[2:0]:
The exact function of these three READ/WRITE bit-fields
depends upon whether the Receive POS-PHY Interface block
has been configured to operate in the Packet or Chunk Mode, as
described below.
If the Receive POS-PHY Interface block is operating in the
Chunk Mode
If the user has configured the Receive POS-PHY Interface block
to operate in the Chunk Mode, then these three bit-fields permit
the user to define the size of Chunks within the incoming Packet
data-stream. The following table presents the relationship
between the contents of these three bit-fields and the corre-
sponding size of the fix-sized chunks that exist within the incom-
ing PPP packet data-stream.
Chunk_Size[2:0]
000
001
010
011
100
101
11X
Number of Bytes/Chunk
4 Bytes
8 Bytes
16 Bytes
32 Bytes
64 Bytes
128 Bytes
Not Valid
If the Receive POS-PHY Interface block is operating in the
Packet Mode
If the user has configured the Receive POS-PHY Interface block
to operate in the Packet Mode, then these three bit-fields permit
the user to specify the minimum number of bytes (of Packet
data) that MUST exist within the RxFIFO before the Receive
POS-PHY Interface block will drive the RxPPA output pin "High",
when polled. The following table presents the relationship
between the contents of these three bit-fields and the corre-
sponding number of packet data bytes (within the RxFIFO) that
are required to assert the RxPPA output pin.
RxFIFO Packet
Fill Level[2:0]
000
001
010
011
100
101
110
111
Number of Packet Bytes required
(within RxFIFO) to Assert RxPPA
1 Bytes
2 Bytes
4 Bytes
8 Bytes
16 Bytes
32 Bytes
64 Bytes
128 Bytes
48