XRT79L71_1 Datasheet, PDF (260/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
7-0
Test Cell Error
Count[31:24]
TYPE
RUR
DESCRIPTION
Test Cell Error Count[31:24]:
These RESET-upon-READ bit-fields along with that within the
Receive ATM Cell Processor Block - Test Cell Error Count Reg-
isters - Bytes 2 through 0 contains the 32-bit expression for the
number of Test Cell Bit Errors that have been detected (by the
Test Cell Receiver) since the last read of these registers.
More specifically, these register bits reflect the number of bit
errors that have been detected within the PRBS data that is
transported via the Payload Bytes of these Test Cells, since the
last read of these registers.
This particular register byte contains the MSB (Most Significant
Byte) of this 32-bit value for the number of Test Cell Bit Errors.
NOTES:
1. This register byte is only valid if the Test Cell Receiver
has been enabled.
2. If the number of Test Cell Error Bits reaches the value
"0xFFFFFFFF" then these registers will saturate to and
remain at this value (e.g., it will not overflow to
"0x00000000").
Receive ATM Cell Processor Block - Test Cell Error Count Registers - Byte 2 (Address = 0x1725)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Test Cell
Error
Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Test Cell Error
Count[23:16]
TYPE
RUR
DESCRIPTION
Test Cell Error Count[23:16]:
These RESET-upon-READ bit-fields along with that within the
Receive ATM Cell Processor Block - Test Cell Error Count Reg-
isters - Bytes 3, 1 and 0 contains the 32-bit expression for the
number of Test Cell Bit Errors that have been detected (by the
Test Cell Receiver) since the last read of these registers.
More specifically, these register bits reflect the number of bit
errors that have been detected within the PRBS data that is
transported via the Payload Bytes of these Test Cells, since the
last read of these registers.
NOTES:
1. This register byte is only valid if the Test Cell Receiver
has been enabled.
2. If the number of Test Cell Error Bits reaches the value
"0xFFFFFFFF" then these registers will saturate to and
remain at this value (e.g., it will not overflow to
"0x00000000").
251