XRT79L71_1 Datasheet, PDF (120/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
2
Change in LOF Defect
Condition Interrupt Status
1
Change in LOS Defect
Condition Interrupt Status
TYPE
RUR
RUR
DESCRIPTION
Change in LOF (Loss of Frame) Defect Condition Interrupt
Status:
This RESET-upon-READ bit-field indicates whether or not the
Change in LOF Defect Condition Interrupt has occurred since
the last read of this register.If this interrupt is enabled, then the
Receive E3 Framer block will generate the Change in LOF
Defect Condition Interrupt will occur in response to the following
events.
• Whenever the Receive E3 Framer block declares the LOF
Defect Condition.
• Whenever the Receive E3 Framer block clears the LOF
Defect Condition.
0 - Indicates that the Change in LOF Defect Condition Interrupt
has not occurred since the last of this register.
1 - Indicates that the Change in LOF Defect Condition Interrupt
has occurred since the last read of this register.
NOTE:
The user can determine the current state of the LOF
Defect Condition by reading out the contents of Bit 6
(LOF Defect Condition Declared) within the Receive E3
Configuration and Status Register # 2 - G.832 (Address
= 0x1111).
Change in LOS (Loss of Signal) Defect Condition Interrupt
Status:
This RESET-upon-READ bit-field indicates whether or not the
Change in LOS Defect Condition Interrupt has occurred since
the last read of this register.
If this interrupt is enabled, then the Receive E3 Framer block will
generate the Change in LOS Defect Condition Interrupt will
occur in response to the following events.
• Whenever the Receive E3 Framer block declares the LOS
Defect Condition.
• Whenever the Receive E3 Framer block clears the LOS
Defect Condition.
0 - Indicates that the Change in LOS Defect Condition Interrupt
has not occurred since the last of this register.
1 - Indicates that the Change in LOS Defect Condition Interrupt
has occurred since the last read of this register.
NOTE:
The user can determine the current state of the LOS
Defect Condition by reading out the contents of Bit 4
(LOS Defect Condition Declared) within the Receive E3
Configuration and Status Register # 2 - G.832 (Address
= 0x1111).
111