XRT79L71_1 Datasheet, PDF (192/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
PMON Parity/P-Bit Error Count Register - MSB (Address = 0x1154)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
PMON_Parity_Error_Count_Upper_Byte[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
REV. 1.0.0
BIT 0
RUR
0
BIT NUMBER
NAME
7-0
PMON_P-Bit/Parity Bit
Error_Count_Upper
Byte[7:0]
TYPE
RUR
DESCRIPTION
Performance Monitor - P Bit/Parity Bit Error Count - Upper
Byte:
These RESET-upon-READ bits, along with that within the PMON
P-Bit/Parity Bit Error Count Register - LSB combine to reflect the
cumulative number of P bit errors (for DS3 applications) or BIP-
8/BIP-4 errors (for E3 applications) that have been detected by
the Receive DS3/E3 Framer block, since the last read of this
register. This register contains the Most Significant byte of this
16-bit expression.
PMON Parity/P-Bit Error Count Register - LSB (Address = 0x1155)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
PMON_Parity_Error_Count_Lower_Byte[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
BIT NUMBER
NAME
7-0
PMON_P-Bit/Parity Bit
Error_Count_Lower
Byte[7:0]
TYPE
RUR
DESCRIPTION
Performance Monitor - P Bit/Parity Bit Error Count - Lower
Byte:
These RESET-upon-READ bits, along with that within the PMON
P-Bit/Parity Bit Error Count Register - MSB combine to reflect
the cumulative number of P bit errors (for DS3 applications) or
BIP-8/BIP-4 errors (for E3 applications) that have been detected
by the Receive DS3/E3 Framer block, since the last read of this
register. This register contains the Least Significant byte of this
16-bit expression.
PMON FEBE Event Count Register - MSB (Address = 0x1156)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PMON_FEBE_Event_Count_Upper_Byte[7:0]
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
183