XRT79L71_1 Datasheet, PDF (197/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
7-0
PMON_PLCP -
FEBE_Event_Count_Up
per _Byte[7:0]
TYPE
RUR
DESCRIPTION
Performance Monitor - PLCP FEBE Event Count Register -
Upper Byte:
These RESET-upon-READ bits, along with that within the PMON
PLCP FEBE Event Count Register - LSB combine to reflect the
cumulative number of PLCP FEBE events that have been
detected by the Receive PLCP Processor block, since the last
reads of this register. This register contains the Most Significant
byte of this 16-bit expression.
NOTE: These register bits are only active if the XRT79L71 has
been configured to operate in both the ATM UNI and
PLCP Modes.
PMON PLCP FEBE Event Count Register - LSB (Address = 0x115F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
PMON_PLCP - FEBE_Event_Count_Lower_Byte[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
PMON_PLCP -
FEBE_Event_Count_Lo
wer _Byte[7:0]
RUR
Performance Monitor - PLCP FEBE Event Count Register -
Lower Byte:
These RESET-upon-READ bits, along with that within the PMON
PLCP FEBE Event Count Register - MSB combine to reflect the
cumulative number of PLCP FEBE events that have been
detected by the Receive PLCP Processor block, since the last
reads of this register. This register contains the Least Significant
byte of this 16-bit expression.
These register bits are only active if the XRT79L71 has been
configured to operate in both the ATM UNI and PLCP Modes.
THE PRBS ERROR COUNT REGISTERS
A NOTE ABOUT READING OUT THE CONTENTS OF THE PRBS ERROR COUNT REGISTERS
The PRBS Error Count Registers (below) are 16-bit RESET-upon-READ registers. However, the manner in
which these registers are to be read is listed below.
As mentioned earlier, these Registers are 16-bits in length. More specifically these registers will consist of a
MSB (Most Significant Byte) 8-bit register, and a LSB (Least Significant Byte) register. Since the
Microprocessor Interface of the XRT79L71 contains an eight-bit wide bi-directional data bus, the user will have
to execute two consecutive read operations in order to obtain the full 16-bit contents of these PRBS Error
Count Registers. As the user reads out the contents of these Registers, the user must be aware of the
following restrictions.
• During the first (of the two) read operations (to the PRBS Error Count Registers), the user read out either the
MSB or the LSB Register.
• However, as the user executes this first read operation, the entire 16-bit contents of this particular PRBS
Error Count Register will be cleared to "0x0000". The XRT79L71 will store the contents of the un-read
register into the PMON Holding Register (Address = 0x116C).
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