XRT79L71_1 Datasheet, PDF (166/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
0
F Bit Mask [0]/X Bit # 1
TYPE
R/W
DESCRIPTION
Transmit F-Bit Error - Bit 1/X Bit # 1:
The exact function of this register bit depends upon the following
parameters.
• Whether the XRT79L71 has been configured to operate in the
Clear-Channel Framer Mode, or not.
• Whether Bit 7 (TxOHSrc), within the Test Register (Address =
0x110C) is set to "1" or "0".
If the XRT79L71 is NOT configured to operate in the Clear-
Channel Framer Mode, OR if TxOHSrc = "0" - Transmit F-Bit
Error - Bit 1:
This READ/WRITE bit-field permits the user to configure the
Transmit DS3 Framer block to transmit DS3 frames with an
erred F bit.
This F-bit corresponds with the 1st F-bit, within a given outbound
DS3 frame. The Transmit DS3 Framer block will perform an
XOR operation with the contents of this bit-field and value of the
1st F-bit. The results of this calculation will be written back into
the 1st F-bit position, within each outbound DS3 frame.
The user should set this bit-field to "0" for normal (e.g., un-erred)
operation.
If the XRT79L71 is configured to operate in the Clear-Chan-
nel Framer Mode, AND if TxOHSrc = "1" - Insert Enable for X
Bit # 1:
This READ/WRITE bit-field permits the user to configure the
Transmit Payload Data Input Interface block to externally accept
an overhead bit and insert it into the X-Bit # 1 bit-field, within the
outbound DS3 data-stream.
0 - Configures the Transmit Direction circuitry to externally
accept and insert data into this overhead bit-field.
1- Configures the Transmit Direction circuitry to NOT externally
accept and insert data into this overhead bit-field.
Transmit DS3 Pattern Register (Address = 0x114C)
BIT 7
BIT 6
BIT 5
BIT 4
TxAIS
Unframed
"All-Ones"
DS3 AIS
Non-Stuck
Stuff
Unused
TxLOS
Pattern
Select
R/W
R/W
R/O
R/W
0
0
0
0
BIT 3
R/W
1
BIT 2
BIT 1
Transmit_Idle_Pattern[3:0]
R/W
R/W
1
0
BIT 0
R/W
0
157