XRT79L71_1 Datasheet, PDF (289/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

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XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
7-0
User Cell Filter # 1 - Pat-
tern Register - Header
Byte 3
TYPE
R/W
DESCRIPTION
User Cell Filter # 1 - Pattern Register - Header Byte 3:
The User Cell filtering criteria (for User Cell Filter # 1) is defined
based upon the contents of 9 read/write registers. These regis-
ters are the four Receive ATM Cell Processor Block - Receive
User Cell Filter # 1 - Pattern Registers, the four Receive ATM
Cell Processor Block - Receive User Cell Filter # 1 - Check Reg-
isters and the Receive ATM Cell Processor Block - Receive User
Cell Filter # 1 Control Register.
This READ/WRITE register, along with the Receive ATM Cell
Processor Block - Receive User Cell Filter # 1 - Check Register -
Header Byte 3 permits the user to define the User Cell Filtering
criteria for Octet # 3 of the incoming User Cell. The user will
write the header byte pattern (for Octet 3) that the user wishes to
use as part of the User Cell Filtering criteria, into this register.
The user will also write in a value into the Receive ATM Cell Pro-
cessor Block - Receive User Cell Filter # 1 - Check Register -
Header Byte 3 that indicates which bits within the first octet of
the incoming cells are to be compared with the contents of this
register.
Receive ATM Cell Processor Block - Receive User Cell Filter # 1 - Pattern Register - Header Byte 4
(Address = 0x1757)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
User Cell Filter # 1 - Pattern Register - Byte 4 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
User Cell Filter # 1 - Pat-
tern Register - Header
Byte 4
TYPE
R/W
DESCRIPTION
User Cell Filter # 1 - Pattern Register - Header Byte 4:
The User Cell filtering criteria (for User Cell Filter # 1) is defined
based upon the contents of 9 read/write registers. These regis-
ters are the four Receive ATM Cell Processor Block - Receive
User Cell Filter # 1 - Pattern Registers, the four Receive ATM
Cell Processor Block - Receive User Cell Filter # 1 - Check Reg-
isters and the Receive ATM Cell Processor Block - Receive User
Cell Filter # 1 Control Register.
This READ/WRITE register, along with the Receive ATM Cell
Processor Block - Receive User Cell Filter # 1 - Check Register -
Header Byte 4 permits the user to define the User Cell Filtering
criteria for Octet # 4 of the incoming User Cell. The user will
write the header byte pattern (for Octet 4) that the user wishes to
use as part of the User Cell Filtering criteria, into this register.
The user will also write in a value into the Receive ATM Cell Pro-
cessor Block - Receive User Cell Filter # 1 - Check Register -
Header Byte 4 that indicates which bits within the first octet of
the incoming cells are to be compared with the contents of this
register.
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