XRT79L71_1 Datasheet, PDF (372/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
7-0
Transmit - Discard Cell
Count[7:0]
TYPE
RUR
DESCRIPTION
Transmit - Discard Cell Count - Byte 0[7:0]:
This RESET-upon-READ register, along with the Transmit ATM
Cell Processor Block - Transmit ATM Cell Discard Cell Count -
Bytes 3 through 1 registers, contain a 32-bit value for the num-
ber of ATM cells that have been discarded by the Transmit ATM
Cell Processor block.
This particular register contains the LSB (Least Significant Byte)
value of this 32-bit expression.
NOTES:
1. The contents within these register includes all ATM
cells that contain either a HEC Byte error or a Transmit
UTOPIA Parity error.
2. If the number of Cells reaches the value
"0xFFFFFFFFF" then these registers will saturate to
and remain at this value (e.g., it will NOT overflow to
"0x00000000").
Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Byte 3 (Address =
0x1F30)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit - HEC Byte Error Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Transmit - HEC Byte
Error Count[31:24]
TYPE
RUR
DESCRIPTION
Transmit - HEC Byte Error Count - Byte 3[7:0]:
This RESET-upon-READ register, along with the Transmit ATM
Cell Processor Block - Transmit ATM HEC Byte Error Count
Register - Bytes 2 through 0 register, contain a 32-bit value for
the number of ATM cells that contain HEC byte errors (as
detected by the Transmit ATM Cell Processor block).
This particular register functions as the MSB (Most Significant
Byte) for this 32-bit expression.
NOTES:
1. This register is valid if the Transmit ATM Cell Processor
block has been configured to compute and verify the
HEC byte of each ATM cell that it receives from the
TxFIFO or the Transmit Cell Insertion Buffer.
2. If the number of cells reaches the value "0xFFFFFFFF",
then these registers will saturate to and remain at this
value (e.g., it will NOT overflow to "0x00000000").
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