XRT79L71_1 Datasheet, PDF (398/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
7-0
Transmit User Cell Filter
# 1 - Check Register -
Header Byte 3
TYPE
R/W
DESCRIPTION
Transmit User Cell Filter # 1 - Check Register - Header Byte
3:
The User Cell filtering criteria (for Transmit User Cell Filter # 1) is
defined based upon the contents of 9 read/write registers.
These registers are the four Transmit ATM Cell Processor Block
- Transmit User Cell Filter # 1 - Pattern Registers, the four Trans-
mit ATM Cell Processor Block - Transmit User Cell Filter # 1 -
Check Registers and the Transmit ATM Cell Processor Block -
Transmit User Cell Filter # 1 Control Register.
This READ/WRITE register, along with the Transmit ATM Cell
Processor Block - Transmit User Cell Filter # 1 - Pattern Register
- Header Byte 3 permits the user to define the User Cell Filtering
criteria for Octet # 3 within the incoming User Cell. More specifi-
cally, these READ/WRITE register bits permit the user to specify
which bit(s) in Octet 3 of the incoming user cell (in the Transmit
ATM Cell Processor Block) are to be checked against the corre-
sponding bit-fields within the Transmit ATM Cell Processor Block
- Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3
by the User Cell Filter, when determine whether to filter a given
User Cell.
Writing a "1" to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the correspond-
ing bit in Octet # 3 (of the incoming user cell) with the corre-
sponding bit in the Transmit ATM Cell Processor Block -
Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3.
Writing a "0" to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
Octet # 3 (in the incoming user cell) as a don't care (e.g., to forgo
the comparison between the corresponding bit in Octet # 3 of the
incoming user cell with the corresponding bit-field in the Transmit
ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pat-
tern Register - Header Byte 3).
Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Byte 4 (Address =
0x1F5B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit User Cell Filter # 1 - Check Register - Byte 4 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
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