XRT79L71_1 Datasheet, PDF (259/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

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XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
7-0
Receive Test Cell Header
Byte 3 [7:0]
TYPE
R/W
DESCRIPTION
Receive Test Cell Header Byte 3:
These READ/WRITE register bits along with that in Receive
ATM Cell Processor Block - Receive Test Cell Header Byte -
Bytes 1, 2 and 4 permit the user to define the header bytes of
test cells that are being generated by the Transmit Test Cell
Generator. These cells also permit the Receive Test Cell
Receiver to identify the test cells within the incoming ATM cell
data stream.
This particular register byte permits the user to define the con-
tents of Header byte # 3.
NOTE: These register bits are only valid if the Receive Test Cell
Receiver has been enabled.
Receive ATM Cell Processor Block - Receive Test Cell Header Byte - Byte 4 (Address = 0x1723)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive Test Cell Header Byte 4[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-0
Receive Test Cell Header
Byte 4 [7:0]
TYPE
R/W
DESCRIPTION
Receive Test Cell Header Byte 4:
These READ/WRITE register bits along with that in Receive
ATM Cell Processor Block - Receive Test Cell Header Byte -
Bytes 1 through 3 permit the user to define the header bytes of
test cells that are being generated by the Transmit Test Cell
Generator. These cells also permit the Receive Test Cell
Receiver to identify the test cells within the incoming ATM cell
data stream.
This particular register byte permits the user to define the con-
tents of Header byte # 4.
NOTE: These register bits are only valid if the Receive Test Cell
Receiver has been enabled.
Receive ATM Cell Processor Block - Test Cell Error Count Registers - Byte 3 (Address = 0x1724)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Test Cell Error Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
250