XRT79L71_1 Datasheet, PDF (344/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
Transmit ATM Cell Processor Block - Transmit ATM Control - Byte 0 (Address = 0x1F03)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
HEC Byte
Invert
HEC Byte
Check
Enable
Transmit
UTOPIA
Parity Check
Enable
Transmit
UTOPIA
Parity Error -
Discard
Transmit
UTOPIA -
ODD Parity
Reserved
R/W
R/W
R/W
R/W
R/W
R/O
R/O
0
0
0
0
0
0
0
BIT 0
Scrambler
Enable
R/W
0
BIT NUMBER
NAME
7
HEC Byte Invert
6
HEC Byte Check Enable
5
Transmit UTOPIA Parity
Check Enable
TYPE
R/W
R/W
R/W
DESCRIPTION
HEC Byte Invert:
This READ/WRITE bit-field permits the user to configure the
Transmit ATM Cell Processor block to invert each bit within the
newly computed HEC byte of each outbound ATM cell.
0 - Configures the Transmit ATM Cell Processor block to NOT
invert the HEC byte values that it inserts into the fifth octet posi-
tion within each outbound ATM cell.
1 - Configures the Transmit ATM Cell Processor block to invert
each bit-field within the newly computed HEC, prior to inserting it
into the fifth octet position, within each outbound ATM cell.
HEC Byte Check Enable:
This READ/WRITE bit-field permits the user to configure the
Transmit ATM Cell Processor block to perform HEC byte check-
ing of all ATM cells that it receives via the Transmit UTOPIA
Interface block.
0 - Configures the Transmit ATM Cell Processor block to NOT
perform HEC byte checking on all ATM cells that it receives via
the Transmit UTOPIA Interface block.
1 - Configures the Transmit ATM Cell Processor block to perform
HEC byte checking on all ATM cells that it receives via the
Transmit UTOPIA Interface block.
Transmit UTOPIA Parity Check Enable:
This READ/WRITE bit-field permits the user to either enable or
disable Transmit UTOPIA Interface Parity checking. If the user
enables Transmit UTOPIA Interface Parity Checking, then the
Transmit ATM Cell Processor block will compute either the
EVEN or ODD parity value (depending upon the setting of Bit 3
within this register) of each byte or 16-bit word that is input via
the Transmit UTOPIA Data Bus input pins: (TxUData[15:0]).
Afterwards, the Transmit ATM Cell Processor block will compare
this locally computed parity value with that which the ATM Layer
Processor has provided to the TxUPrty input pin. If the Transmit
ATM Cell Processor detects any discrepancies between these
two parity values (e.g., any parity errors) then it will take action
based upon the user's settings for Bit 4 (Transmit UTOPIA Parity
Error - Discard).
0 - Disables Transmit UTOPIA Interface Parity Checking.
1 - Enables Transmit UTOPIA Interface Parity Checking.
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