XRT79L71_1 Datasheet, PDF (92/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT NUMBER
NAME
3
RxFEACRemove Inter-
rupt Enable
2
RxFEAC Remove Inter-
rupt Status
1
RxFEAC Valid Interrupt
Enable
0
RxFEAC Valid Interrupt
Status
TYPE
R/W
RUR
R/W
RUR
DESCRIPTION
FEAC Message Remove Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the Receive FEAC Remove Interrupt. If the user enables
this interrupt, then the Receive DS3/E3 Framer block will gener-
ate an interrupt anytime the most recently validated FEAC Mes-
sage has been removed. The Receive FEAC Controller will
remove a validated FEAC codeword, if it has received a different
codeword in 3 out of the last 10 FEAC Messages
.0 - Receive FEAC Remove Interrupt is disabled.
1 - Receive FEAC Remove Interrupt is enabled.
NOTE: This bit-field is only active if the XRT79L71 has been
configured to operate in the DS3, C-bit Parity Framing
format.
FEAC Message Remove Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
FEAC Message Remove Interrupt has occurred since the last
read of this register.
0 - FEAC Message Remove Interrupt has NOT occurred since
the last read of this register.
1 - FEAC Message Remove Interrupt has occurred since the last
read of this register.
NOTE: This bit-field is only active if the XRT79L71 has been
configured to operate in the DS3, C-bit Parity Framing
format.
FEAC Message Validation Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the FEAC Message Validation Interrupt. If the user
enables this interrupt, then the Receive DS3/E3 Framer block
will generate an interrupt anytime a new FEAC Codeword has
been validated by the Receive FEAC Controller block.
0 - FEAC Message Validation Interrupt is NOT enabled.
1 - FEAC Message Validation Interrupt is enabled.
NOTE: This bit-field is only active if the XRT79L71 has been
configured to operate in the DS3, C-bit Parity Framing
format.
FEAC Message Validation Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
FEAC Message Validation Interrupt has occurred since the last
read of this register.
0 - FEAC Message Validation Interrupt has not occurred since
the last read of this register.
1 - FEAC Message Validation Interrupt has occurred since the
last read of this register.
NOTE: This bit-field is only active if the XRT79L71 has been
configured to operate in the DS3, C-bit Parity Framing
format.
83