XRT79L71_1 Datasheet, PDF (205/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

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XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT
NUMBER
NAME
6
HDLC Controller
Enable
TYPE
DESCRIPTION
R/W HDLC Controller Enable:
This READ/WRITE bit-field configures the XRT79L71 to operate in either the
High-Speed HDLC Controller Mode, or in the Clear-Channel Framer Mode.
If the user configures the XRT79L71 to operate in the High-Speed HDLC
Controller Mode, then all of the following will be true.
In the Transmit Direction
Some of the Transmit Payload Data Input Interface pins will change function,
and will present a byte-wide Transmit High-Speed HDLC Controller input
interface to the System-Side Terminal Equipment. This Transmit High-Speed
HDLC Controller input interface will also present the System-Side Terminal
Equipment with a demand output clock signal (which is approximately one-
eight of the either the E3 or DS3 rates, depending which rate is being used).
This Transmit High-Speed HDLC Controller Input Interface will accept data
(from the System-Side Terminal Equipment) in a byte-wide manner. As the
Transmit High-Speed HDLC Controller Input Interface accepts this data, it will
route this data to the Transmit High-Speed HDLC Controller block where it
will encapsulate this data into a variable-length HDLC frame. The Transmit
High-Speed HDLC Controller block will also take on the responsibility of zero-
stuffing the payload data, within each of these outbound HDLC frames.
Finally, the Transmit High-Speed HDLC Controller circuitry will optionally
append either a CRC-32 or CRC-16 value to the back-end of any outbound
HDLC frame.
Anytime the System-Side Terminal Equipment is NOT providing any data to
the Transmit High-Speed HDLC Controller Input Interface, then the Transmit
High-Speed HDLC Controller block will generate a string of repeating Flag
Sequence octets (0x7E), in order to (1) denote the boundaries of all outbound
HDLC frames and (2) to indicate that no HDLC frames are currently being
transported across the DS3/E3 transport medium.
This composite outbound data-stream (consisting of HDLC frames and Flag
Sequence octets) will be routed to the Transmit DS3/E3 Framer block. In this
case, the Transmit DS3/E3 Framer block will insert this composite outbound
data-stream into the payload bits within each outbound DS3 or E3 data-
stream.
In the Receive Direction
In the Receive Direction, the Receive High-Speed HDLC Controller block will
accept the payload data (within the incoming DS3/E3 data-stream) from the
Receive DS3/E3 Framer block. As the Receive High-Speed HDLC Controller
block receives this incoming data, it will perform the following functions.
• It will flag any occurrence of the Flag Sequence octet, within the incoming
data-stream..
• It will locate the boundaries of the incoming HDLC frames.
• It will perform zero-unstuffing on the payload data (within each incoming
HDLC frame).
• It will compute and verify either the CRC-16 or CRC-32 value (that is
appended at the back-end of the outbound HDLC Frame).
• It will output this incoming HDLC data to the System-Side Terminal
Equipment via a byte-wide output interface.
0 - Configures the XRT79L71 to operate in the Clear-Channel Framer Mode
(e.g., disables the Transmit and Receive High-Speed HDLC Controller
blocks).
1 - Configures the XRT79L71 to operate in the High-Speed HDLC Controller
(e.g., enables the Transmit and Receive High-Speed HDLC Controller
blocks).
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