XRT79L71_1 Datasheet, PDF (245/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

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XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
BIT NUMBER
NAME
6
Receive FIFO Overflow
Interrupt Enable
5
Receive Cell Extraction
Memory Overflow Inter-
rupt Enable
4
Receive Cell Insertion
Memory Overflow Inter-
rupt Enable
3
Detection of Correctable
HEC Byte Error Interrupt
Enable
TYPE
R/W
R/W
R/W
R/W
DESCRIPTION
Receive FIFO Overflow Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the Receive FIFO Overflow Interrupt.
If the user enables this interrupt, then the Receive ATM Cell Pro-
cessor block will generate an interrupt any time an overflow con-
dition occurs within the RxFIFO.
0 - Disables the Receive FIFO Overflow Interrupt.
1 - Enables the Receive FIFO Overflow Interrupt.
Receive Cell Extraction Memory Overflow Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the Receive Cell Extraction Memory Overflow Interrupt.
If the user enables this interrupt, then the Receive ATM Cell Pro-
cessor block will generate an interrupt any time an overflow
event has occurred in the Receive Cell Extraction Memory
buffer.
0 - Disables the Receive Cell Extraction Memory Overflow Inter-
rupt.
1 - Enables the Receive Cell Extraction Memory Overflow Inter-
rupt.
Receive Cell Insertion Memory Overflow Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the Receive Cell Insertion Memory Overflow Interrupt.
If the user enables this interrupt, then the Receive ATM Cell Pro-
cessor block will generate an interrupt any time an overflow
event has occurred in the Receive Cell Insertion Memory buffer.
0 - Disables the Receive Cell Insertion Memory Overflow Inter-
rupt.
1 - Enables the Receive Cell Insertion Memory Overflow Inter-
rupt.
Detection of Correctable HEC Byte Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the Detection of Correctable HEC Byte Error Interrupt
within the Receive ATM Cell Processor block.
If the user enables this interrupt, then the Receive ATM Cell Pro-
cessor block will generate an interrupt each time it receives an
ATM cell (in incoming traffic) that contains a correctable HEC
Byte error.
0 - Disables the Detection of Correctable HEC Byte Error Inter-
rupt.
1 - Enables the Detection of Correctable HEC Byte Error Inter-
rupt.
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