XRT79L71_1 Datasheet, PDF (228/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
REV. 1.0.0
BIT
NUMBER
3
NAME
Jitter Attenuator FIFO
Pointer RESET
TYPE
R/W
2
Jitter Attenuator PLL/ R/W
FIFO Operating Mode -
Bit 1
DEFAULT
VALUE
0
0
DESCRIPTION
Jitter Attenuator RESET:
Writing a "0" to "1" transition within this bit-field will config-
ure the Jitter Attenuator (within the XRT79L71) to execute a
RESET operation.
Whenever the user executes a RESET operation, then all of
the following will occur.
• The READ and WRITE pointers (within the Jitter
Attenuator FIFO) will be reset to their default values.
• The contents of the Jitter Attenuator FIFO will be flushed.
NOTE: The user must follow up any "0" to "1" transition with
the appropriate write operate to set this bit-field
back to "0", in order to resume normal operation
with the Jitter Attenuator.
Jitter Attenuator Configuration Select Input - Bit 1:
This READ/WRITE bit-field, along with Bit 0 (JA0) permits
the user to do any of the following.
• To enable or disable the Jitter Attenuator within the
XRT79L71.
• To select the FIFO Depth for the Jitter Attenuator within
the XRT79L71.
The relationship between the settings of these two bit-fields
and the Enable/Disable States, and FIFO Depths is pre-
sented
below.
JA0 JA1
Jitter Attenuator Mode
0
0 Enabled FIFO Depth = 16 bits
0
1 Enabled FIFO Depth = 32 bits
1
0
Disabled
1
1
Disabled
1
Jitter Attenuator in
R/W
Transmit Path
0
Jitter Attenuator PLL/ R/W
FIFO Operating Mode
- Bit 0
0
Jitter Attenuator in Transmit/Receive Path Select Bit:
This input pin permits the user to configure the Jitter Attenu-
ator (within the XRT79L71) to operate in either the Transmit
or Receive path, as described below.
0 - Configures the Jitter Attenuator (e.g., within the Receive
DS3/E3 LIU Block) to operate in the Receive Path.
1 - Configures the Jitter Attenuator (e.g., within the Receive
DS3/E3 LIU Block) to operate in the Transmit Path.
0
Jitter Attenuator Configuration Select Input - Bit 0:
Please see the description for Bit 2 (JA1) within this Regis-
ter.
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