XRT79L71_1 Datasheet, PDF (81/434 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -

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XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION
Payload HDLC Control Register, Address = 0x110D
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Framer
By-Pass
HDLC
Controller
Enable
HDLC
CRC-32
Unused
HDLC
Loop-back
R/W
R/W
R/W
R/O
R/W
0
0
0
0
0
BIT 2
R/O
0
BIT 1
Unused
R/O
0
BIT 0
R/O
0
BIT NUMBER
NAME
7
Framer By-Pass
6
HDLC Controller Enable
TYPE
R/W
R/W
DESCRIPTION
HDLC Controller Enable:
This READ/WRITE bit-field configures the XRT79L71 to operate
in either the High-Speed HDLC Controller Mode, or in the Clear-
Channel Framer Mode.
If the user configures the XRT79L71 to operate in the High-
Speed HDLC Controller Mode, then all of the following will be
true
In the Transmit Direction
Some of the Transmit Payload Data Input Interface pins will
change function, and will present a byte-wide Transmit High-
Speed HDLC Controller input interface to the System-Side Ter-
minal Equipment. This Transmit High-Speed HDLC Controller
input interface will also present the System-Side Terminal Equip-
ment with a demand output clock signal (which is approximately
one-eight of the either the E3 or DS3 rates, depending which
rate is being used).
This Transmit High-Speed HDLC Controller Input Interface will
accept data (from the System-Side Terminal Equipment) in a
byte-wide manner. As the Transmit High-Speed HDLC Control-
ler Input Interface accepts this data, it will route this data to the
Transmit High-Speed HDLC Controller block where it will encap-
sulate this data into a variable-length HDLC frame. The Trans-
mit High-Speed HDLC Controller block will also take on the
responsibility of zero-stuffing the payload data, within each of
these outbound HDLC frames. Finally, the Transmit High-Speed
HDLC Controller circuitry will optionally append either a CRC-32
or CRC-16 value to the back-end of any Outbound HDLC frame.
Anytime the System-Side Terminal Equipment is NOT providing
any data to the Transmit High-Speed HDLC Controller Input
Interface, then the Transmit High-Speed HDLC Controller block
will generate a string of repeating Flag Sequence octets (0x7E),
in order to (1) denote the boundaries of all outbound HDLC
frames and (2) to indicate that no HDLC frames are currently
being transported across the DS3/E3 transport medium.
This composite Outbound data-stream (consisting of HDLC
frames and Flag Sequence octets) will be routed to the Transmit
DS3/E3 Framer block. In this case, the Transmit DS3/E3
Framer block will insert this composite Outbound data-stream
into the payload bits within each outbound DS3 or E3 data-
stream.
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